Many conventional memories, such as random access memories (RAMs) and read-only memories (ROMs) of various types (including ROMs, PROMs, EPROMs, and EEPROMs), are intended to operate in a static mode, where presentation of an address to the memory accesses the desired memory location, without requiring a clock signal. For most static memories, no maximum cycle time is specified (in contrast to dynamic memories such as dynamic RAMs), so that the memory must respond whenever a change in address is presented. One way in which such operation is achieved is by providing a "fully" static memory, where all circuitry within the memory is operating so long as the chip is enabled; for example, the addresses may be statically decoded, so that the value at the address pins is continually being decoded.
In modern computing systems which use such memories, however, power dissipation of the memories is of concern. Fully static memories, since all circuitry internal is operating at all times, thus dissipate significantly more power than a similarly sized dynamic memory. Accordingly, many conventional static memories have low-power modes, such as standby modes, where the contents of the memory are maintained but where the peripheral circuitry is disabled, saving significant power.
One conventional way in which some static memories enter such a low-power mode is through the use of "time-out" circuitry, usually in combination with an address or input transition detection circuit. A time-out circuit within such memories disables certain peripheral functions within the memory after a time period has elapsed since the beginning of the prior memory operation; the address transition detection circuit remains enabled, generates an internal signal upon detection of a change of address (i.e., a new memory cycle is being enabled), and re-enables the memory.
Referring to FIG. 1, a conventional time-out circuit 100 as used in static RAM devices is illustrated. Time-out circuit 100 receives inputs on lines ATD.sub.n-- from a number of address transition detection circuits (not shown), and on line DTD.sub.-- from a data transition detection circuit (also not shown); the inputs on lines ATD.sub.n-- are summed by NAND gate 102 and inverted by inverter 103, and presented to one input of NAND gate 104, which also receives line DTD.sub.-- at an input. The output of NAND gate 104 is connected to a push-pull driver including p-channel transistor 105, p-channel transistor 107, and n-channel transistors 106 having their source-drain paths connected in series between V and ground. The gates of transistors 105 and 107 receive the output of NAND gate 104, and p-channel transistor 107 has its gate tied to ground, serving as a resistive element as will be shown hereinbelow. The drains of transistors 106 and 107 are connected to the input of inverter 109, which drives line TO at its output; a latching p-channel transistor is connected between the drain of transistors 105 and the input of inverter 109, and has its gate connected to the output of inverter 109. It should be noted that this conventional circuit also can communicate the presence of an address transition to other portions of the memory, as suggested by the precharge control circuit 110 receiving the output of NAND gate 102, and presenting a precharge signal on line PC responsive thereto.
In operation, beginning in the disabled condition, all lines ATD.sub.n-- and DTD.sub.-- are high, which sets the output of NAND gate 104 to a low logic level, pulling high the input of inverter 109 through transistors 105 and 107, and setting line TO low. In this condition, line TO is indicating to the remainder of the memory within which circuit 100 is incorporated that certain of the peripheral circuits can be disabled, such as decoders, sense amplifiers, write drivers and the like; in such a condition, certain circuits remain activated, however, examples of which include output drivers, and possibly equilibration and precharge devices for the bit lines of the memory. Upon the initiation of a memory operation, one or more of lines ATD.sub.n-- and line DTD go to a low logic level, causing the output of NAND gate 104 to go to a high logic level. This causes transistor 106 to turn on, pulling the input of inverter 109 low, and issuing a high level on line TO. Since the transition detection circuits issue pulses upon detection of a transition, upon completion of the pulses the output of NAND gate 104 returns to a low logic level, turning on transistor 105 and turning off transistors 106. Due to the resistance presented by transistor 107, however, inverter 109 will not see a high logic level at its input until a certain delay time after the transition detection pulses have ended. Upon the expiration of this delay time, the input of inverter 109 will be pulled high, causing line TO to return to a low logic level, communicating the time-out state, to the remainder of the memory.
Selection of the time delay for time-out circuit 100, or other conventional time-out circuits, determines the amount of power savings achieved in the memory. It is of course essential that the time-out delay from the beginning of the cycle be sufficiently long that completion of the desired operations occur; premature time-out would result in the reading or writing of incorrect data. It is also desirable, however, that the time-out of the memory occur as soon as possible after the completion of the operation, as this would result in the greatest average power savings.
However, different types of cycles require different time periods to perform their operation, prior to timing out. For example, a write operation generally takes longer than a read operation in many modern memories. Accordingly, since the time-out cannot occur until such time as a write operation is complete, conventional memories have selected the time-out time based on the worst case operation. As a result, the selected worst case time-out delay period results in unnecessary dissipation of power in read operations.
It is therefore an object of this invention to provide a memory where the time-out delay period is optimized for each type of memory cycle.
It is a further object of this invention to provide a time-out circuit for a memory which times out earlier in a read cycle than in a write cycle.
It is a further object of this invention to provide such a circuit having separately established time-out delays for read operations than for write operations.
It is a further object of this invention to allow for fast enabling of the periphery after a timed-out write operation, responsive to a data transition.